1. Field of the Invention
The present invention relates to a bus line wiring structure and a method of manufacturing the same that connects overlapping bus line layers with an intervening insulation layer between them, and more particularly, to a bus line wiring structure between a gate line and another line in a micro electrical device having a plurality of thin film transistors (TFTs) such as a liquid crystal display (LCD) device, a memory device, or a non-memory semiconductor device.
2. Discussion of the Related Art
In semiconductor fabrication, it is very important to maximize the number of TFTs that are integrated per unit area in a high density, micro-sized semiconductor device, such as a high resolution LCD device. In order to design a memory device having a higher capacitance or a higher resolution LCD device than an XGA (eXtended video Graphic Array) device, the number of TFTs per unit area must be increased. Thus, the bus lines connected with the TFTs are designed to be disposed in smaller spaces. Therefore, the space for connecting the gate line of the TFT and another line must be reduced.
The conventional method for connecting the bus lines formed in a separate layer to the wiring structure is shown in FIGS. 1a-2d. Specifically, FIG. 1a shows a cross sectional view of the connection for bus lines formed in a separate layer according to the conventional method, FIG. 1b shows the plan view of the wiring structure according to the conventional method, and FIGS. 2a-2d show the steps of the conventional manufacturing process.
As shown in FIG. 2a, a metal, such as aluminum or an aluminum alloy, is deposited on a substrate 11. The metal layer is patterned to form a low resistance gate line 15a. The surface of the low resistance gate line 15a is easily susceptible to hillock growth problem. The hillock growth is formed by being enlarged a grain of aluminum on the surface under high temperature during the following depositing processor such as an insulating layer depositing. The hillock of Al can be growing at 300.degree. C. or higher. Generally, the aluminum is deposited about 200.degree. C., so the hillock of Al can not be growing during the formation of the aluminum layer. However, the insulating layer is deposited at about 390.degree. C. So, when the insulating layer is deposited the hillocks of Al can be growing. A metal, such as chromium or molybdenum, is deposited on the substrate 11. The metal layer is patterned to form a gate line 15 covering the low resistance gate line 15a. The gate line 15 prevents the hillock problem from occurring in the low resistance gate line 15a.
As shown in FIG. 2b, an insulation material such as silicon oxide or silicon nitride is deposited on the substrate having the gate line 15 to form a gate insulation layer 19. A metal, such as chromium or a chromium alloy, is deposited on the gate insulation layer 19. The metal layer is patterned to form a source line 35. The source line 35 is connected with the source electrode of the switching elements, such as a TFT.
As shown in FIG. 2c, an insulating material, such as a silicon nitride or a silicon oxide, is deposited on the substrate having the source line 35 to form a protection layer 39. The gate line 15 and the source line 35 are disposed on the separated layer with the intervening gate insulation layer 19 between them. Here, the gate line 15 and the source line 35 must not be connected to each other because they are used for different objects. However, they can be connected to each other as needed during some of the processing steps to protect them from static electricity. In addition, if a repair line for source line 35 is formed in the same layer and with the same material of the gate line 15, then the source line 35 should be connected to the repair line.
In order to connect the source line 35 and the gate line 15 (or the repair line in the same layer of the gate line 15), a gate contact hole 41 and a source contact hole 51 are formed, as shown in FIG. 2c. That is, at least a portion of a gate line 15 is exposed by etching the protection layer 39 and the gate insulation layer 19 to form the gate contact hole 41. Also, at least a portion of the source line 35 is exposed by etching the protection layer 39 to form the source contact hole.
As shown in FIG. 2d, a conductive material, such as an indium tin oxide (ITO), is deposited on the protection layer 39. The ITO layer is patterned to form a connecting terminal 53. The connecting terminal 53 connects the gate line 15 and the source line 35 through the gate contact hole 41 and the source contact hole 51.
In the conventional method for connecting the bus lines, the lines are connected by a third conductive material through the contact holes arrayed in horizontal. Hence, space is needed for the contact holes, thereby limiting the density of the semiconductor device. For example, in manufacturing a high density semiconductor device, all elements in the device are made smaller. Accordingly, the width of the gate line and the source line correspondingly becomes narrower. Furthermore, the number of connecting parts is increased, thereby hindering the reduction of the connection area.